Sciweavers

211 search results - page 21 / 43
» REDEFIS: a system with a redefinable instruction set process...
Sort
View
DAC
2009
ACM
14 years 8 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
LCPC
2004
Springer
14 years 29 days ago
Speculative Subword Register Allocation in Embedded Processors
Abstract. Multimedia and network processing applications make extensive use of subword data. Since registers are capable of holding a full data word, when a subword variable is ass...
Bengu Li, Youtao Zhang, Rajiv Gupta
CGO
2006
IEEE
14 years 1 months ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
ASPDAC
2000
ACM
109views Hardware» more  ASPDAC 2000»
13 years 11 months ago
A technique for QoS-based system partitioning
Quality of service (QoS) has been an important topic of many research communities. Combined with an advanced and retargetable compiler, variability of applicationsspecific very lar...
Johnson S. Kin, Chunho Lee, William H. Mangione-Sm...
SC
1992
ACM
13 years 11 months ago
Compiler Code Transformations for Superscalar-Based High Performance Systems
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
Scott A. Mahlke, William Y. Chen, John C. Gyllenha...