211 search results - page 38 / 43 » REDEFIS: a system with a redefinable instruction set process... |
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
TJS
2002
13 years 7 months ago
2002
Historically, compilers have operated by applying a fixed set of optimizations in a predetermined order. We call such an ordered list of optimizations a compilation sequence. This...
SOSP
2009
ACM
14 years 4 months ago
2009
ACM
Commodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instructio...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
Since software is playing an increasingly important role in systemon-chip, retargetable compilation has been an active research area in the last few years. However, the retargetti...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...