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MICRO
2006
IEEE
73views Hardware» more  MICRO 2006»
15 years 10 months ago
Merging Head and Tail Duplication for Convergent Hyperblock Formation
VLIW and EDGE (Explicit Data Graph Execution) architectures rely on compilers to form high-quality hyperblocks for good performance. These compilers typically perform hyperblock f...
Bertrand A. Maher, Aaron Smith, Doug Burger, Kathr...
SBACPAD
2006
IEEE
148views Hardware» more  SBACPAD 2006»
15 years 10 months ago
Scalable Parallel Implementation of Bayesian Network to Junction Tree Conversion for Exact Inference
We present a scalable parallel implementation for converting a Bayesian network to a junction tree, which can then be used for a complete parallel implementation for exact inferen...
Vasanth Krishna Namasivayam, Animesh Pathak, Vikto...
VTS
2006
IEEE
93views Hardware» more  VTS 2006»
15 years 10 months ago
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
ADVIS
2006
Springer
15 years 10 months ago
A Network-Based Indexing Method for Trajectories of Moving Objects
Recently many researchers have focused on management of historical trajectories of moving objects due to numerous size of accumulated data over time. However, most of them are conc...
Kyoung-Sook Kim, Mario A. Lopez, Scott T. Leuteneg...
ASPDAC
2006
ACM
119views Hardware» more  ASPDAC 2006»
15 years 10 months ago
Using speculative computation and parallelizing techniques to improve scheduling of control based designs
Recent research results have seen the application of parallelizing techniques to high-level synthesis. In particular, the effect of speculative code transformations on mixed contr...
Roberto Cordone, Fabrizio Ferrandi, Marco D. Santa...