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» Rationale and Design of BULK
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CSREAESA
2003
13 years 11 months ago
Common Mistakes in Adiabatic Logic Design and How to Avoid Them
Most so-called “adiabatic” digital logic circuit families reported in the low-power design literature are actually not truly adiabatic, in that they do not satisfy the general...
Michael P. Frank
NJC
2006
125views more  NJC 2006»
13 years 9 months ago
PRO: A Model for the Design and Analysis of Efficient and Scalable Parallel Algorithms
Abstract. We present a new parallel computation model called the Parallel ResourceOptimal computation model. PRO is a framework being proposed to enable the design of efficient and...
Assefaw Hadish Gebremedhin, Mohamed Essaïdi, ...
NSDI
2004
13 years 11 months ago
Designing a DHT for Low Latency and High Throughput
Designing a wide-area distributed hash table (DHT) that provides high-throughput and low-latency network storage is a challenge. Existing systems have explored a range of solution...
Frank Dabek, Jinyang Li, Emil Sit, James Robertson...
NSDI
2007
13 years 12 months ago
WiLDNet: Design and Implementation of High Performance WiFi Based Long Distance Networks
WiFi-based Long Distance (WiLD) networks with links as long as 50–100 km have the potential to provide connectivity at substantially lower costs than traditional approaches. How...
Rabin K. Patra, Sergiu Nedevschi, Sonesh Surana, A...
ISLPED
2003
ACM
71views Hardware» more  ISLPED 2003»
14 years 2 months ago
Strained-si devices and circuits for low-power applications
Static and dynamic power for strained-Si device is analyzed and compared with conventional bulk-Si technology. Optimum device design points are suggested with controlling physical...
Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang