Strained-si devices and circuits for low-power applications

Static and dynamic power for strained-Si device is analyzed and compared with conventional bulk-Si technology. Optimum device design points are suggested with controlling physical/structural device parameters. Strained-Si CMOS circuits are studied, showing substantially-reduced power consumptions due to unique advantageous features of strainedSi device. The trade-offs for power and performance in strained-Si devices/circuits are discussed. Further, analysis and low-power design points are applied and extended to strained Si on SOI substrate (SSOI) CMOS technology. Categories and Subject Descriptors B.7.1 [Hardware]: Integrated Circuits–Types and Design Style General Terms Design, Theory, Verification Keywords Strained-Si MOSFET, SOI, SiGe, Mobility, Band offset

• Type: Conference
• Year: 2003
• Where: ISLPED
• Authors: Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang
• Keywords: Design Points, Device Design Points, ISLPED 2003, Physical/structural Device Parameters