Sciweavers

213 search results - page 42 / 43
» ReConfigME: a detailed implementation of an operating system...
Sort
View
ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
14 years 11 days ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
IWOMP
2007
Springer
14 years 1 months ago
Supporting OpenMP on Cell
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Ton...
PPOPP
2010
ACM
14 years 4 months ago
Is transactional programming actually easier?
Chip multi-processors (CMPs) have become ubiquitous, while tools that ease concurrent programming have not. The promise of increased performance for all applications through ever ...
Christopher J. Rossbach, Owen S. Hofmann, Emmett W...
GECCO
2005
Springer
232views Optimization» more  GECCO 2005»
14 years 19 days ago
A hardware pipeline for function optimization using genetic algorithms
Genetic Algorithms (GAs) are very commonly used as function optimizers, basically due to their search capability. A number of different serial and parallel versions of GA exist. ...
Malay Kumar Pakhira, Rajat K. De
DSN
2003
IEEE
14 years 12 days ago
Dependability Enhancement for IEEE 802.11 Wireless LAN with Redundancy Techniques
The presence of physical obstacles and radio interference results in the so called “shadow regions” in wireless networks. When a mobile station roams into a shadow region, it ...
Dongyan Chen, Sachin Garg, Chandra M. R. Kintala, ...