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» Reasoning about Memory Layouts
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VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 3 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
SAS
2010
Springer
262views Formal Methods» more  SAS 2010»
13 years 8 months ago
Concurrent Separation Logic for Pipelined Parallelization
Recent innovations in automatic parallelizing compilers are showing impressive speedups on multicore processors using shared memory with asynchronous channels. We have formulated a...
Christian J. Bell, Andrew W. Appel, David Walker
SOFTVIS
2010
ACM
13 years 10 months ago
Embedding spatial software visualization in the IDE: an exploratory study
Software visualization can be of great use for understanding and exploring a software system in an intuitive manner. Spatial representation of software is a promising approach of ...
Adrian Kuhn, David Erni, Oscar Nierstrasz
SP
2009
IEEE
155views Security Privacy» more  SP 2009»
14 years 4 months ago
A Logic of Secure Systems and its Application to Trusted Computing
We present a logic for reasoning about properties of secure systems. The logic is built around a concurrent programming language with constructs for modeling machines with shared ...
Anupam Datta, Jason Franklin, Deepak Garg, Dilsun ...
ISCA
1998
IEEE
123views Hardware» more  ISCA 1998»
14 years 2 months ago
Weak Ordering - A New Definition
A memory model for a shared memory, multiprocessor commonly and often implicitly assumed by programmers is that of sequential consistency. This model guarantees that all memory ac...
Sarita V. Adve, Mark D. Hill