174 search results - page 34 / 35 » Reclocking for high-level synthesis |
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
We propose REWIRED (REgister Write Inhibition by REsource Dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of fun...
ISTA
2008
13 years 9 months ago
2008
This contribution suggests a novel approach for a systematic generation of a process model in an informal environment. It is based on the claim that the knowledge about the process...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
RE
1997
Springer
13 years 11 months ago
1997
Springer
The field of requirements engineering emerges out of tradition of research and engineering practice that stresses rtance of generalizations and abstractions. abstraction is essent...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...