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IJCV
2000
133views more  IJCV 2000»
13 years 7 months ago
Heteroscedastic Regression in Computer Vision: Problems with Bilinear Constraint
We present an algorithm to estimate the parameters of a linear model in the presence of heteroscedastic noise, i.e., each data point having a different covariance matrix. The algor...
Yoram Leedan, Peter Meer
AIPR
2008
IEEE
13 years 9 months ago
Low-cost, high-speed computer vision using NVIDIA's CUDA architecture
In this paper, we introduce real time image processing techniques using modern programmable Graphic Processing Units (GPU). GPUs are SIMD (Single Instruction, Multiple Data) device...
Seung In Park, Sean P. Ponce, Jing Huang, Yong Cao...
FPL
1998
Springer
135views Hardware» more  FPL 1998»
13 years 11 months ago
Designing for Xilinx XC6200 FPGAs
With the XC6200 FPGA Xilinx introduced the first commercially available FPGA designed for reconfigurable computing. It has a completely new internal architecture, so new design alg...
Reiner W. Hartenstein, Michael Herz, Frank Gilbert
FPGA
2006
ACM
156views FPGA» more  FPGA 2006»
13 years 11 months ago
A reconfigurable architecture for network intrusion detection using principal component analysis
In this paper, we develop an architecture for principal component analysis (PCA) to be used as an outlier detection method for high-speed network intrusion detection systems (NIDS...
David T. Nguyen, Gokhan Memik, Alok N. Choudhary
ASPDAC
1995
ACM
116views Hardware» more  ASPDAC 1995»
13 years 11 months ago
A datapath synthesis system for the reconfigurable datapath architecture
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto...
Reiner W. Hartenstein, Rainer Kress