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TVLSI
2008
133views more  TVLSI 2008»
13 years 9 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
ISCA
2000
IEEE
118views Hardware» more  ISCA 2000»
14 years 18 days ago
Smart Memories: a modular reconfigurable architecture
Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and lo...
Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, Willi...
BROADNETS
2006
IEEE
14 years 23 days ago
SMART: An Optical Infrastructure for Future Internet
A new scalable optical network infrastructure SMART is proposed based on light-trails and hypernetwork architecture. The underlying physical network of SMART is a reconfigurable WD...
Si-Qing Zheng, Ashwin Gumaste
HOTI
2008
IEEE
14 years 3 months ago
Adaptive Routing Strategies for Modern High Performance Networks
Today’s scalable high-performance applications heavily depend on the bandwidth characteristics of their communication patterns. Contemporary multi-stage interconnection networks...
Patrick Geoffray, Torsten Hoefler
ISCAS
2003
IEEE
129views Hardware» more  ISCAS 2003»
14 years 2 months ago
SONICmole: a debugging environment for the UltraSONIC reconfigurable computer
Reconfigurable Computers based on a combination of conventional microprocessors and Field Programmable Gate Arrays (FPGAs) presents new challenges to designers. Debugging on such ...
Theerayod Wiangtong, Chun Te Ewe, Peter Y. K. Cheu...