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DATE
2005
IEEE
110views Hardware» more  DATE 2005»
14 years 4 months ago
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration
attributed to the high regularity of memories, PAs and FPGAs, and the ease with which they can be tested and reconfigured to avoid faulty elements. Digital microfluidicsbased bioch...
Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula
DAC
2002
ACM
14 years 11 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
ERSA
2007
194views Hardware» more  ERSA 2007»
14 years 9 days ago
A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture
Abstract: If the computational demands of an interactive graphics rendering application cannot be met by a single commodity Graphics Processing Unit (GPU), multiple graphics accele...
Ross Brennan, Michael Manzke, Keith O'Conor, John ...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 7 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
JNSM
2010
166views more  JNSM 2010»
13 years 5 months ago
High-Level Design Approach for the Specification of Cognitive Radio Equipments Management APIs
Cognitive Radio (CR) equipments are radio devices that support the smart facilities offered by future cognitive networks. Even if several categories of equipments exist (terminal,...
Christophe Moy