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» Reconfigurable trusted computing in hardware
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ERSA
2007
86views Hardware» more  ERSA 2007»
13 years 9 months ago
High-Precision BLAS on FPGA-enhanced Computers
The emergence of high-density reconfigurable hardware devices gives scientists and engineers an option to accelerating their numerical computing applications on low-cost but power...
Chuan He, Guan Qin, Richard E. Ewing, Wei Zhao
IPPS
1998
IEEE
13 years 11 months ago
A Configurable Computing Approach Towards Real-Time Target Tracking
Traditionally, tracking systems require dedicated hardware to handle the computational demands and input/output rates imposed by real-time video sources. An alternative presented i...
Bharadwaj Pudipeddi, A. Lynn Abbott, Peter M. Atha...
ISCA
1999
IEEE
96views Hardware» more  ISCA 1999»
13 years 11 months ago
PipeRench: A Coprocessor for Streaming multimedia Acceleration
Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes ...
Seth Copen Goldstein, Herman Schmit, Matthew Moe, ...
MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
13 years 7 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
DAC
2006
ACM
13 years 11 months ago
IMPRES: integrated monitoring for processor reliability and security
Security and reliability in processor based systems are concerns requiring adroit solutions. Security is often compromised by code injection attacks, jeopardizing even `trusted so...
Roshan G. Ragel, Sri Parameswaran