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FCCM
2000
IEEE
122views VLSI» more  FCCM 2000»
14 years 1 months ago
Evaluating Hardware Compilation Techniques
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...
Markus Weinhardt, Wayne Luk
VLSID
2004
IEEE
209views VLSI» more  VLSID 2004»
14 years 9 months ago
An Architecture for Motion Estimation in the Transform Domain
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, ...
HPCC
2010
Springer
13 years 8 months ago
A Generic Algorithm Template for Divide-and-Conquer in Multicore Systems
The divide-and-conquer pattern of parallelism is a powerful approach to organize parallelism on problems that are expressed naturally in a recursive way. In fact, recent tools such...
Carlos H. Gonzalez, Basilio B. Fraguela
ERSA
2010
182views Hardware» more  ERSA 2010»
13 years 6 months ago
Integrating Application Specification and Performance Prediction for Strategic Design-Space Exploration
Abstract--Modeling environments and performance prediction boost application productivity, but often lack integration into an efficient and comprehensive approach to strategic desi...
Brian Holland, Alan D. George, Herman Lam
3DPVT
2006
IEEE
233views Visualization» more  3DPVT 2006»
14 years 2 months ago
Scanline Optimization for Stereo on Graphics Hardware
In this work we propose a scanline optimization procedure for computational stereo using a linear smoothness cost model performed by programmable graphics hardware. The main idea ...
Christopher Zach, Mario Sormann, Konrad F. Karner