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GLVLSI
2000
IEEE
85views VLSI» more  GLVLSI 2000»
14 years 3 months ago
Fast and accurate estimation of floorplans in logic/high-level synthesis
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh
IEEEPACT
2000
IEEE
14 years 3 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
14 years 3 months ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan
HASE
1998
IEEE
14 years 3 months ago
Analytical Partition of Software Components for Evolvable and Reliable MEMS Design Tools
Transforming software requirements into a software design involves the iterative partition of a solution into software components. The process is human-intensive and does not guar...
Carol L. Hoover, Pradeep K. Khosla
ISPD
1998
ACM
244views Hardware» more  ISPD 1998»
14 years 3 months ago
Analysis, reduction and avoidance of crosstalk on VLSI chips
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
Tilmann Stöhr, Markus Alt, Asmus Hetzel, J&uu...