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FCCM
2000
IEEE
122views VLSI» more  FCCM 2000»
14 years 1 months ago
Evaluating Hardware Compilation Techniques
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...
Markus Weinhardt, Wayne Luk
DAC
2009
ACM
14 years 10 months ago
O-Router:an optical routing framework for low power on-chip silicon nano-photonic integration
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, D...
ASAP
2007
IEEE
136views Hardware» more  ASAP 2007»
14 years 3 months ago
0/1 Knapsack on Hardware: A Complete Solution
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
K. Nibbelink, S. Rajopadhye, R. McConnell
WAIM
2005
Springer
14 years 2 months ago
Extracting, Presenting and Browsing of Web Social Information
We address the problem that current Web applications present mainly the content-centric information, but lack cues and browsing mechanisms for online social information. After summ...
Yi Wang, Li-Zhu Zhou
FPL
2009
Springer
79views Hardware» more  FPL 2009»
14 years 1 months ago
A reconfigurable architecture for the Phylogenetic Likelihood Function
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run effici...
Nikolaos Alachiotis, Alexandros Stamatakis, Euripi...