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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
13 years 12 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
DEXA
2008
Springer
176views Database» more  DEXA 2008»
13 years 9 months ago
Inventing Less, Reusing More, and Adding Intelligence to Business Process Modeling
Recently, a variety of workflow patterns has been proposed focusing on specific aspects like control flow, data flow, and resource assignments. Though these patterns are relevant f...
Lucinéia Heloisa Thom, Manfred Reichert, Ca...
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 4 months ago
Formal model of data reuse analysis for hierarchical memory organizations
– In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhan...
Ilie I. Luican, Hongwei Zhu, Florin Balasa
ASIAMS
2007
IEEE
14 years 1 months ago
On Syntactic Composability and Model Reuse
Composability, the capability to select and assemble offthe-shelf model components in various combinations to satisfy user requirements, is an appealing approach in reducing the t...
Claudia Szabo, Yong Meng Teo
ICMCS
2006
IEEE
152views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Reuse of Motion Processing for Camera Stabilization and Video Coding
The low bit rate of existing video encoders relies heavily on the accuracy of estimating actual motion in the input video sequence. In this paper, we propose a Video Stabilization...
Bao Lei, Rene Klein Gunnewiek, Peter H. N. de With