31 search results - page 3 / 7 » Reduced Latency IEEE Floating-Point Standard Adder Architect... |
ICPP
1999
IEEE
14 years 25 days ago
1999
IEEE
Loops are the main time consuming part of programs based on floating point computations. The performance of the loops is limited either by recurrences in the computation or by the...
ISCA
2012
IEEE
11 years 11 months ago
2012
IEEE
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
ISQED
2008
IEEE
14 years 2 months ago
2008
IEEE
Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This i...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
SBACPAD
2007
IEEE
14 years 2 months ago
2007
IEEE
Adoption of the 10GbE Ethernet standard has been impeded by two important performance-oriented considerations: 1) processing requirements of common protocol stacks and 2) end-to-e...