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» Reducibility and Completeness in Private Computations
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HPCA
2009
IEEE
14 years 10 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
IWCMC
2006
ACM
14 years 3 months ago
A novel broadcast technique for high-density ad hoc networks
Broadcasting in ad hoc networks is required for many routing and other network-layer protocols to request information like routes or locations about destination nodes. Most of the...
Ai Hua Ho, Alexander J. Aved, Kien A. Hua
HIPEAC
2005
Springer
14 years 3 months ago
Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture
Abstract. Designers of large parallel computers and clusters are becoming increasingly concerned with the cost and power consumption of the interconnection network. A simple way to...
Pedro Javier García, Jose Flich, José...
DAC
2010
ACM
14 years 1 months ago
LUT-based FPGA technology mapping for reliability
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
Jason Cong, Kirill Minkovich
SIAMMAX
2010
189views more  SIAMMAX 2010»
13 years 4 months ago
Fast Algorithms for the Generalized Foley-Sammon Discriminant Analysis
Linear Discriminant Analysis (LDA) is one of the most popular approaches for feature extraction and dimension reduction to overcome the curse of the dimensionality of the high-dime...
Lei-Hong Zhang, Li-Zhi Liao, Michael K. Ng