5 search results - page 1 / 1 » Reducing Cache Conflicts by Multi-Level Cache Partitioning a... |
ICPADS
2000
IEEE
14 years 2 months ago
2000
IEEE
DSD
2010
IEEE
13 years 11 months ago
2010
IEEE
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
ICS
2005
Tsinghua U.
14 years 4 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
ISCA
2009
IEEE
14 years 5 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
PARELEC
2006
IEEE
14 years 5 months ago
2006
IEEE
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...