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» Reducing Compilation Time Overhead in Compiled Simulators
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ICNP
2009
IEEE
13 years 5 months ago
Memory Efficient Protocols for Detecting Node Replication Attacks in Wireless Sensor Networks
Sensor networks deployed in hostile areas are subject to node replication attacks, in which an adversary compromises a few sensors, extracts the security keys, and clones them in a...
Ming Zhang, Vishal Khanapure, Shigang Chen, Xuelia...
EWC
2008
117views more  EWC 2008»
13 years 8 months ago
Performance of parallel computations with dynamic processor allocation
In parallel adaptive mesh refinement (AMR) computations the problem size can vary significantly during a simulation. The goal here is to explore the performance implications of dyn...
Saeed Iqbal, Graham F. Carey
DATE
2009
IEEE
189views Hardware» more  DATE 2009»
14 years 2 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
CGO
2007
IEEE
14 years 2 months ago
Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications
Run-time compilation systems are challenged with the task of translating a program’s instruction stream while maintaining low overhead. While software managed code caches are ut...
Vijay Janapa Reddi, Dan Connors, Robert Cohn, Mich...
STORAGESS
2005
ACM
14 years 1 months ago
An electric fence for kernel buffers
Improper access of data buffers is one of the most common errors in programs written in assembler, C, C++, and several other languages. Existing programs and OSs frequently acces...
Nikolai Joukov, Aditya Kashyap, Gopalan Sivathanu,...