663 search results - page 104 / 133 » Reducing Compilation Time Overhead in Compiled Simulators |
SPAA
2006
ACM
14 years 2 months ago
2006
ACM
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial an...
ICA3PP
2010
Springer
14 years 27 days ago
2010
Springer
Abstract. Deploying lightweight tasks on grid resources would let the communication overhead dominate the overall application processing time. Our aim is to increase the resulting ...
RTAS
2005
IEEE
14 years 1 months ago
2005
IEEE
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
UCS
2007
Springer
14 years 2 months ago
2007
Springer
Abstract. We propose D-FLER, a distributed, general-purpose reasoning engine for WSN. D-FLER uses fuzzy logic for fusing individual and neighborhood observations, in order to produ...