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» Reducing Compilation Time Overhead in Compiled Simulators
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DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 1 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
CN
2010
121views more  CN 2010»
13 years 4 months ago
Probabilistic flooding for efficient information dissemination in random graph topologies
Probabilistic flooding has been frequently considered as a suitable dissemination information approach for limiting the large message overhead associated with traditional (full) f...
Konstantinos Oikonomou, Dimitrios Kogias, Ioannis ...
DSN
2002
IEEE
14 years 1 months ago
Ditto Processor
Concentration of design effort for current single-chip Commercial-Off-The-Shelf (COTS) microprocessors has been directed towards performance. Reliability has not been the primary ...
Shih-Chang Lai, Shih-Lien Lu, Jih-Kwon Peir
BROADNETS
2007
IEEE
14 years 2 months ago
Scheduling routing table calculations to achieve fast convergence in OSPF protocol
Fast convergence to topology changes is a key requirement in modern routing infrastructure while reducing the protocol CPU overhead continues to be as important as before. In this...
Mukul Goyal, Weigao Xie, Mohd Soperi, Seyed H. Hos...
HPCA
2009
IEEE
14 years 8 months ago
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches
As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...
Mainak Chaudhuri