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» Reducing Compilation Time Overhead in Compiled Simulators
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PLDI
2000
ACM
14 years 6 days ago
Field analysis: getting useful and low-cost interprocedural information
We present a new limited form of interprocedural analysis called field analysis that can be used by a compiler to reduce the costs of modern language features such as objectorien...
Sanjay Ghemawat, Keith H. Randall, Daniel J. Scale...
IEEEPACT
1997
IEEE
14 years 2 days ago
A Parallel Algorithm for Compile-Time Scheduling of Parallel Programs on Multiprocessors
† In this paper, we propose a parallel randomized algorithm, called Parallel Fast Assignment using Search Technique (PFAST), for scheduling parallel programs represented by direc...
Yu-Kwong Kwok, Ishfaq Ahmad
ASPLOS
1992
ACM
13 years 12 months ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 1 months ago
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Rui Rodrigues, João M. P. Cardoso
MTDT
2003
IEEE
105views Hardware» more  MTDT 2003»
14 years 1 months ago
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu L...