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» Reducing Compilation Time Overhead in Compiled Simulators
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CC
2011
Springer
270views System Software» more  CC 2011»
12 years 11 months ago
Subregion Analysis and Bounds Check Elimination for High Level Arrays
For decades, the design and implementation of arrays in programming languages has reflected a natural tension between productivity and performance. Recently introduced HPCS langua...
Mackale Joyner, Zoran Budimlic, Vivek Sarkar
LCTRTS
2010
Springer
14 years 25 days ago
Cache vulnerability equations for protecting data in embedded processor caches from soft errors
Continuous technology scaling has brought us to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, cac...
Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul
ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
14 years 1 months ago
Efficient Simulation of Synthesis-Oriented System Level Designs
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
IFIP
2010
Springer
13 years 2 months ago
A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement
Abstract. In this article, we present a flexible simulation environment for embedded real-time software refinement by a mixed level cosimulation. For this, ne the native speed of a...
Markus Becker, Henning Zabel, Wolfgang Müller...
TON
1998
87views more  TON 1998»
13 years 7 months ago
Adaptive hybrid clock discipline algorithm for the network time protocol
This paper describes the analysis, implementation and performance of a new algorithm engineered to discipline a computer clock to a source of standard time, such as a GPS receiver...
David L. Mills