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» Reducing Compilation Time Overhead in Compiled Simulators
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PPOPP
2012
ACM
12 years 3 months ago
Deterministic parallel random-number generation for dynamic-multithreading platforms
Existing concurrency platforms for dynamic multithreading do not provide repeatable parallel random-number generators. This paper proposes that a mechanism called pedigrees be bui...
Charles E. Leiserson, Tao B. Schardl, Jim Sukha
EMSOFT
2010
Springer
13 years 6 months ago
Optimal WCET-aware code selection for scratchpad memory
We propose the first polynomial-time code selection algorithm for minimising the worst-case execution time of a nonnested loop executed on a fully pipelined processor that uses sc...
Hui Wu, Jingling Xue, Sridevan Parameswaran
HIPC
2005
Springer
14 years 1 months ago
Cooperative Instruction Scheduling with Linear Scan Register Allocation
Abstract. Linear scan register allocation is an attractive register allocation algorithm because of its simplicity and fast running time. However, it is generally felt that linear ...
Khaing Khaing Kyi Win, Weng-Fai Wong
DATE
2003
IEEE
97views Hardware» more  DATE 2003»
14 years 1 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
CASES
2004
ACM
14 years 1 months ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh