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PDPTA
2003
13 years 8 months ago
2003
The performance of the data memory hierarchy is extremely important in current and near future high performance superscalar microprocessors. To address the memory gap, computer de...
ISCA
2009
IEEE
14 years 1 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Applications from the embedded consumer domain put challenging requirements on SoC infrastructures, i.e. interconnect and memory. Specifically, video applications demand large sto...
ISCAPDCS
2004
13 years 8 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
LCTRTS
2007
Springer
14 years 25 days ago
2007
Springer
As mobile phones become increasingly multifunctional, the number and size of applications installed in phones are rapidly increasing. Consequently, mobile phones require more hard...