Comparing Multiported Cache Schemes

The performance of the data memory hierarchy is extremely important in current and near future high performance superscalar microprocessors. To address the memory gap, computer designers implement caches to reduce the high memory latencies that are observed in the processor. Due to the ever increasing instruction window sizes and issue widths in new microprocessor designs, designers will need to implement multiported caches in order to be able service multiple memory requests per clock cycle. Several studies have been conducted in previous work dealing with the performance in terms of Instructions Per Cycle (IPC) for such cache designs. However, little is known about the access time, the energy consumption and the required chip area for multiported caches. This paper quantifies these aspects for several multiported cache designs.

• Type: Conference
• Year: 2003
• Where: PDPTA
• Authors: Smaïl Niar, Lieven Eeckhout, Koenraad De Bosschere
• Keywords: Cache Designs, Data Memory Hierarchy, Multiported Cache, PDPTA 2003, PDPTA 2007