155 search results - page 15 / 31 » Reducing Design Complexity of the Load Store Queue |
IEEEPACT
2006
IEEE
14 years 2 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
HPCA
1998
IEEE
14 years 9 days ago
1998
IEEE
The explosive growth in the performance of microprocessors and networks has created a new opportunity to reduce the latency of fine-grain communication. Microprocessor clock speed...
IPPS
1998
IEEE
14 years 9 days ago
1998
IEEE
A number of solutions have been proposed for the problem of mutual exclusion in distributed systems. Some of these approaches have since been extended to a prioritized environment...
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, prog...