Sciweavers

437 search results - page 34 / 88
» Reducing Memory Sharing Overheads in Distributed JVMs
Sort
View
OSDI
1996
ACM
13 years 9 months ago
Online Data-Race Detection via Coherency Guarantees
We present the design and evaluation of an on-thefly data-race-detection technique that handles applications written for the lazy release consistent (LRC) shared memory model. We ...
Dejan Perkovic, Peter J. Keleher
ISHPC
2003
Springer
14 years 23 days ago
Improving Memory Latency Aware Fetch Policies for SMT Processors
Abstract. In SMT processors several threads run simultaneously to increase available ILP, sharing but competing for resources. The instruction fetch policy plays a key role, determ...
Francisco J. Cazorla, Enrique Fernández, Al...
IPPS
2009
IEEE
14 years 2 months ago
DMTCP: Transparent checkpointing for cluster computations and the desktop
DMTCP (Distributed MultiThreaded CheckPointing) is a transparent user-level checkpointing package for distributed applications. Checkpointing and restart is demonstrated for a wid...
Jason Ansel, Kapil Arya, Gene Cooperman
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 20 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
PPOPP
2009
ACM
14 years 8 months ago
A compiler-directed data prefetching scheme for chip multiprocessors
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
Dhruva Chakrabarti, Mahmut T. Kandemir, Mustafa Ka...