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CODES
2001
IEEE
14 years 1 months ago
Towards effective embedded processors in codesigns: customizable partitioned caches
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...
Peter Petrov, Alex Orailoglu
ICTAI
1997
IEEE
14 years 1 months ago
Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization
This paper proposes an optimization algorithm for reducing the power dissipation in a sequential circuit. The encoding of the different states in a Finite State Machine is modifie...
S. Chuisano, Fulvio Corno, Paolo Prinetto, Maurizi...
ICPP
1995
IEEE
14 years 1 months ago
The Application of Skewed-Associative Memories to Cache Only Memory Architectures
— Skewed-associative caches use several hash functions to reduce collisions in caches without increasing the associativity. This technique can increase the hit ratio of a cache w...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
WSC
2007
14 years 15 days ago
Feasibility study of variance reduction in the logistics composite model
The Logistics Composite Model (LCOM) is a stochastic, discrete-event simulation that relies on probabilities and random number generators to model scenarios in a maintenance unit ...
George P. Cole III, Alan W. Johnson, J. O. Miller
WSC
2008
14 years 15 days ago
Study of optimal load lock dedication for cluster tools
Cluster or chamber tools are often used in the semiconductor industry. In a research environment, moving to smaller device dimensions requires experimentation with new chamber typ...
Julie Christopher