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» Reducing Parallel Overheads Through Dynamic Serialization
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HPCA
2009
IEEE
14 years 9 months ago
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches
As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...
Mainak Chaudhuri
SIGOPS
2011
215views Hardware» more  SIGOPS 2011»
13 years 3 months ago
Log-based architectures: using multicore to help software behave correctly
While application performance and power-efficiency are both important, application correctness is even more important. In other words, if the application is misbehaving, it is li...
Shimin Chen, Phillip B. Gibbons, Michael Kozuch, T...
ICS
2005
Tsinghua U.
14 years 2 months ago
Transparent caching with strong consistency in dynamic content web sites
We consider a cluster architecture in which dynamic content is generated by a database back-end and a collection of Web and application server front-ends. We study the effect of t...
Cristiana Amza, Gokul Soundararajan, Emmanuel Cecc...
HPCA
2011
IEEE
13 years 13 days ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...
SPAA
2010
ACM
14 years 1 months ago
Lightweight, robust adaptivity for software transactional memory
When a program uses Software Transactional Memory (STM) to synchronize accesses to shared memory, the performance often depends on which STM implementation is used. Implementation...
Michael F. Spear