314 search results - page 60 / 63 » Reducing Parallel Overheads Through Dynamic Serialization |
ICPPW
2007
IEEE
14 years 1 months ago
2007
IEEE
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissi...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scala...
JSAC
2011
13 years 2 months ago
2011
—Driven by both safety concerns and commercial interests, one of the key services offered by vehicular networks is popular content distribution (PCD). The fundamental challenges ...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...