135 search results - page 22 / 27 » Reducing Power Dissipation in SRAM during Test |
FPL
2008
Springer
13 years 9 months ago
2008
Springer
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high b...
ATS
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
CN
2004
13 years 7 months ago
2004
Energy is the most critical resource in the life of a wireless sensor node. Therefore, its usage must be optimized to maximize the network life. It is known that for higher path l...
DAC
2004
ACM
13 years 11 months ago
2004
ACM
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...