135 search results - page 6 / 27 » Reducing Power Dissipation in SRAM during Test |
DFT
2002
IEEE
14 years 17 days ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
TVLSI
2008
13 years 7 months ago
2008
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Many test data compression schemes are based on LFSR reseeding. A drawback of these schemes is that the unspecified bits are filled with random values resulting in a large number ...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
— In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is...
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...