Low Power Test Data Compression Based on LFSR Reseeding

Many test data compression schemes are based on LFSR reseeding. A drawback of these schemes is that the unspecified bits are filled with random values resulting in a large number of transitions during scan-in thereby causing high power dissipation. This paper presents a new encoding scheme that can be used in conjunction with any LFSR reseeding scheme to significantly reduce test power and even further reduce test storage. The proposed encoding scheme acts as a second stage of compression after LFSR reseeding. It accomplishes two goals. First, it reduces the number of transitions in the scan chains (by filling the unspecified bits in a different manner), and second it reduces the number of specified bits that need to be generated via LFSR reseeding. Experimental results indicate that the proposed method significantly reduces test power and in most cases provides greater test data compression than LFSR reseeding alone.

• Type: Conference
• Year: 2004
• Where: ICCD
• Authors: Jinkyu Lee, Nur A. Touba
• Keywords: Hardware, ICCD 2004, LFSR Reseeding Scheme, Test Data Compression, Unspecified Bits