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» Reducing Power in High-Performance Microprocessors
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SIGCOMM
2006
ACM
16 years 18 days ago
Algorithms to accelerate multiple regular expressions matching for deep packet inspection
There is a growing demand for network devices capable of examining the content of data packets in order to improve network security and provide application-specific services. Most...
Sailesh Kumar, Sarang Dharmapurikar, Fang Yu, Patr...
SAMOS
2007
Springer
16 years 23 days ago
Online Prediction of Applications Cache Utility
— General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies a...
Miquel Moretó, Francisco J. Cazorla, Alex R...
166
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ISPASS
2007
IEEE
16 years 28 days ago
An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures
Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploi...
Wangyuan Zhang, Xin Fu, Tao Li, José A. B. ...
206
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CGO
2005
IEEE
16 years 8 days ago
Effective Adaptive Computing Environment Management via Dynamic Optimization
To minimize the surging power consumption of microprocessors, adaptive computing environments (ACEs) where microarchitectural resources can be dynamically tuned to match a program...
Shiwen Hu, Madhavi Gopal Valluri, Lizy Kurian John
ISLPED
2004
ACM
139views Hardware» more  ISLPED 2004»
16 years 2 days ago
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
Kim M. Hazelwood, David Brooks