293 search results - page 40 / 59 » Reducing Power with Performance Constraints for Parallel Spa... |
ITC
2002
IEEE
14 years 18 days ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
CGO
2010
IEEE
14 years 2 months ago
2010
IEEE
Prior work has shown that reduced, ordered, binary decision diagrams (BDDs) can be a powerful tool for program trace analysis and visualization. Unfortunately, it can take hours o...
HIPC
2007
Springer
14 years 1 months ago
2007
Springer
- With the increased complexity of platforms coupled with data centers’ servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for plat...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
– Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based com...
ICIP
2009
IEEE
14 years 8 months ago
2009
IEEE
Enabling parallel processing is becoming increasingly necessary for video decoding as performance requirements continue to rise due to growing resolution and frame rate demands. I...