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» Reducing SoC Simulation and Development Time
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IPCAI
2010
13 years 5 months ago
First Animal Cadaver Study for Interlocking of Intramedullary Nails under Camera Augmented Mobile C-arm
The Camera Augmented Mobile C-arm (CamC) system that augments a regular mobile C-arm by a video camera provides an overlay image of X-ray and video. This technology is expected to ...
Lejing Wang, Jürgen Landes, Simon Weidert, To...
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
14 years 9 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
ISCA
2008
IEEE
130views Hardware» more  ISCA 2008»
14 years 2 months ago
Corona: System Implications of Emerging Nanophotonic Technology
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...
Dana Vantrease, Robert Schreiber, Matteo Monchiero...
KBSE
2005
IEEE
14 years 2 months ago
Automated test generation for engineering applications
In test generation based on model-checking, white-box test criteria are represented as trap conditions written in a temporal logic. A model checker is used to refute trap conditio...
Songtao Xia, Ben Di Vito, César Muño...
CF
2010
ACM
14 years 1 months ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...