39 search results - page 6 / 8 » Reducing bus delay in submicron technology using coding |
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instruct...
ISPD
2004
ACM
14 years 25 days ago
2004
ACM
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
ICDCSW
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract— The wireless mesh network is experiencing tremendous growth with the standardization of IEEE 802.11 and IEEE 802.16 technologies. Compared to its wired counterpart, the...
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...