40 search results - page 4 / 8 » Reducing cache misses through programmable decoders |
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-c...
MICRO
1994
IEEE
13 years 11 months ago
1994
IEEE
Numerical applications frequently contain nested loop structures that process large arrays of data. The execution of these loop structures often produces memory preference pattern...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
PCI
2005
Springer
14 years 1 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
CASES
2010
ACM
13 years 5 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...