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» Reducing cache misses through programmable decoders
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ICS
2005
Tsinghua U.
14 years 1 months ago
Transparent caching with strong consistency in dynamic content web sites
We consider a cluster architecture in which dynamic content is generated by a database back-end and a collection of Web and application server front-ends. We study the effect of t...
Cristiana Amza, Gokul Soundararajan, Emmanuel Cecc...
MICRO
1995
IEEE
102views Hardware» more  MICRO 1995»
13 years 11 months ago
Zero-cycle loads: microarchitecture support for reducing load latency
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
Todd M. Austin, Gurindar S. Sohi
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
13 years 12 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
IEEEPACT
2006
IEEE
14 years 1 months ago
Two-level mapping based cache index selection for packet forwarding engines
Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. The efficiency of a cache for this application critically depends on the ...
Kaushik Rajan, Ramaswamy Govindarajan
JSA
2006
167views more  JSA 2006»
13 years 7 months ago
Pattern-driven prefetching for multimedia applications on embedded processors
Multimedia applications in general and video processing, such as the MPEG4 Visual stream decoders, in particular are increasingly popular and important workloads for future embedd...
Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout