40 search results - page 7 / 8 » Reducing cache misses through programmable decoders |
ICDCS
2007
IEEE
14 years 1 months ago
2007
IEEE
State-of-the-art networked storage servers are equipped with increasingly powerful computing capability and large DRAM memory as storage caches. However, their contribution to the...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Chip multiprocessors (CMPs) substantially increase capacity pressure on the on-chip memory hierarchy while requiring fast access. Neither private nor shared caches can provide bot...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines...
ESTIMEDIA
2004
Springer
14 years 27 days ago
2004
Springer
— Workload design is a well recognized problem in the domain of microprocessor design. Different program characteristics that influence the selection of a representative workloa...
EUROPAR
2003
Springer
14 years 22 days ago
2003
Springer
Hardware performance monitoring is the basis of modern performance analysis tools for application optimization. We are interested in providing such performance analysis tools for t...