42 search results - page 4 / 9 » Reducing cache misses using hardware and software page place... |
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. The efficiency of a cache for this application critically depends on the ...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Virtual caches are employed as L1 caches of both high performance and embedded processors to meet their short latency requirements. However, they also introduce the synonym proble...
ASPLOS
2010
ACM
13 years 11 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
MICRO
1994
IEEE
13 years 11 months ago
1994
IEEE
Numerical applications frequently contain nested loop structures that process large arrays of data. The execution of these loop structures often produces memory preference pattern...
CAL
2010
13 years 5 months ago
2010
Address translation often emerges as a critical performance bottleneck for virtualized systems and has recently been the impetus for hardware paging mechanisms. These mechanisms ap...