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DAC
1996
ACM
13 years 11 months ago
Sizing of Clock Distribution Networks for High Performance CPU Chips
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
Madhav P. Desai, Radenko Cvijetic, James Jensen
ICCAD
2006
IEEE
152views Hardware» more  ICCAD 2006»
14 years 4 months ago
Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression
Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models param...
Zhuo Feng, Peng Li
TGC
2010
Springer
13 years 5 months ago
CarPal: Interconnecting Overlay Networks for a Community-Driven Shared Mobility
Car sharing and car pooling have proven to be an effective solution to reduce the amount of running vehicles by increasing the number of passengers per car amongst medium/big commu...
Vincenzo Dezani-Ciancaglini, Luigi Liquori, Lauren...
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
14 years 1 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
PVLDB
2011
13 years 2 months ago
Column-Oriented Storage Techniques for MapReduce
Users of MapReduce often run into performance problems when they scale up their workloads. Many of the problems they encounter can be overcome by applying techniques learned from ...
Avrilia Floratou, Jignesh M. Patel, Eugene J. Shek...