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VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
14 years 9 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
ICC
2008
IEEE
126views Communications» more  ICC 2008»
14 years 3 months ago
Backlog Aware Scheduling for Large Buffered Crossbar Switches
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...
Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wlad...
SRDS
2006
IEEE
14 years 2 months ago
Topology Sensitive Replica Selection
As the disks typically found in personal computers grow larger, protecting data by replicating it on a collection of “peer” systems rather than on dedicated high performance s...
Dmitry Brodsky, Michael J. Feeley, Norman C. Hutch...
WMPI
2004
ACM
14 years 2 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
ICPP
2002
IEEE
14 years 1 months ago
Design and Evaluation of Scalable Switching Fabrics for High-Performance Routers
This work considers switching fabrics with distributed packet routing to achieve high scalability and low costs. The considered switching fabrics are based on a multistage structu...
Nian-Feng Tzeng, Ravi C. Batchu