Buffered Routing Tree Construction under Buffer Placement Blockages

Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and correcting the timing violations after global placement. This report presents a practical, dynamicprogramming based algorithm for performing net topology construction and buffer insertion and sizing simultaneously under the given buffer placement blockages. The differences from some previous works are that (1) the buffer locations are not pre-determined, (2) the multi-pin nets are easily handled and (3) a line-search based routing algorithm is implemented to speed up the process. Some heuristics are used to reduce the problem complexity. These heuristics include limiting the number of intermediate solutions that we keep, using a continuous buffer sizing method, and restricting the buffer locations along the Hanan graph. This algorithm was applied to a number of real industrial designs and achieved an average ...

• Type: Conference
• Year: 2002
• Where: VLSID
• Authors: Wei Chen, Massoud Pedram, Premal Buch
• Keywords: Buffer Locations, Buffer Placement Blockages, Buffer Sizing Method, Computer Architecture, VLSID 2002