64 search results - page 11 / 13 » Reducing dTLB Energy Through Dynamic Resizing |
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
MDM
2010
Springer
13 years 6 months ago
2010
Springer
—We present an optimal distributed algorithm to adapt the placement of a single operator in high communication cost networks, such as a wireless sensor network. Our parameterfree...
ICPP
2007
IEEE
14 years 1 months ago
2007
IEEE
Performance and power are critical design constraints in today’s high-end computing systems. Reducing power consumption without impacting system performance is a challenge for t...
HIPEAC
2009
Springer
13 years 11 months ago
2009
Springer
Shrinking process technologies and growing chip sizes have profound effects on process variation. This leads to Chip Multiprocessors (CMPs) where not all cores operate at maximum f...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...