152 search results - page 29 / 31 » Reducing dynamic compilation overhead by overlapping compila... |
SIGPLAN
2002
13 years 8 months ago
2002
We present a new analysis for removing unnecessary write barriers in programs that use generational garbage collection. To our knowledge, this is the first static program analysis...
ICCD
2007
IEEE
14 years 16 days ago
2007
IEEE
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
SIGMETRICS
1996
ACM
14 years 24 days ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
PPOPP
2009
ACM
14 years 9 months ago
2009
ACM
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...