21 search results - page 1 / 5 » Reducing memory reference energy with opportunistic virtual ... |
ISCA
2012
IEEE
12 years 1 months ago
2012
IEEE
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
HPCA
2005
IEEE
14 years 11 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
HIPEAC
2007
Springer
14 years 5 months ago
2007
Springer
Abstract. The interest in translation-based virtual execution environments (VEEs) is growing with the recognition of their importance in a variety of applications. However, due to ...
MICRO
1997
IEEE
14 years 3 months ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
ISLPED
2004
ACM
14 years 4 months ago
2004
ACM
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...