221 search results - page 10 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
Both commercial and scientific workloads benefit from concurrency and exhibit data sharing across threads/processes. The resulting sharing patterns are often fine-grain, with t...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissi...
CDES
2008
13 years 9 months ago
2008
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...